Digital data communication systems use a clock signal to transmit or receive data. Systems in which the transmitting device sends the clock signal along with the data to the receiving device are known as source synchronous systems. A problem occurs in high speed source synchronous systems due to the fact that it is difficult to match the printed circuit board trace lengths between the clock and data signals, causing a variable amount of skew between the clock and data signals. To solve this problem, the receiver can use a clock and data recovery (CDR) circuit to adjust the alignment between the received local sampling clock signal and the received data so that the clock signal captures the data when it is most stable, known as the “data eye”. The phase adjustment can be performed by either delaying the clock signal or the data signal until the clock signal transitions approximately in the center of the data eye.
Moreover some data transmission schemes achieve high-speed operation by using small voltage differences between data signals and a reference voltage (referred to as “Vref”). Each bit in the incoming data stream is compared to Vref to determine whether the bit is in the logical “1” or logical “0” state. For example, bits whose voltage is sensed above Vref are interpreted as logical “1” bits and bits with a voltage value below Vref are interpreted as logical “0” bits. To correctly recover the data from the data stream, the receiver needs to accurately generate Vref. Thus, proper reception of data in source synchronous systems requires not only the clock signal to transition when the data signals are in stable states, but also that Vref is accurate.
Different methods have been used to calibrate Vref. One particular method of generating Vref is known as process, voltage and temperature (PVT) shmooing. PVT shmooing entails varying a PVT parameter while keeping all other parameters constant to determine pass or fail values for each setting of the varied parameter. PVT shmooing is repeated across several devices whose processing varies across the manufacturing process window, and choosing a fixed value that is used to set all parts in production. However the fixed value may be sub-optimal for certain parts and across multiple data bits and could increase the bit error rate (BER) of parts processed within acceptable manufacturing tolerances.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.